通信线路的多模式管理外文翻译通信线路的多模式管理外文翻译

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附录二英文文献及译文MULTIMODEMANAGEMENTOFASERIALCOMMUNICATIONLINKBACKGROUNDA.TechnicalFieldThepresentinventionrelatesgenerallytosignalprocessing,andmoreparticularly,tothemanagementofaserialcommunicationlinkbetweentwocomponents,suchasaserializer/deserializerSERDESandatransceiver.B.BackgroundoftheInventionInacommunicationdevice,datacanbetransmittedfromonecomponenttoanothercomponentbyaserialorparalleldatatransfer.Withtherapidimprovementinnetworkingtechnologies,thereisagreatdemandforhighspeedcomponent15tocomponentcommunicationratesinordertomovelargeramountsofdatamoreefficientlywithinanetworkingdevice.Highspeedseriallinksarebeinginterfacedbetweennetworkingcomponentstoachievethesecommunicationrateincreases.Theactualdataratesontheselinksmaybedefinedbyvariousprotocolsandstandards,suchastheSystemPacketInterfaceLevel4SPI4protocolthatcoversaspectrumof622Mb/storatesabove1Gb/s.ASERDESmayinterfaceaparalleldatabuswithaseriallinkbyeffectivelyserializingordeserializingadatasignal.SERDEStechnologyhasbecomeveryimportantasdatarateshavecontinuallyincreasedbecauseaveryfastseriallinkmaybeconvertedtoadeserializedsignalthatcanbemoreeasilytransmittedandprocessedonaparalleldatabus.FIG.1illustratesanexemplarySERDESandinterfacingcomponentsaccordingtooneembodimentoftheinvention.Inthisparticularexample,aSERDES101interfaceseithera64or128bitparallelbus103toaserialdatalink105.Theserialdatalink105isalsocoupledtoatransceiver102.Intheoperationofasystem,therateofthesystemcorelogicmayoperateatadifferentratethantheserialdatalink105becauseoftheparalleltransferofdatatothecorelogic.Inoneexample,theSERDES101serialinterfacereceivesan8bitdatastreamclockedat500MHzandforwardsthedatatothecorelogicina16bitdatastreamclockedat250MHz.TheclockdifferencebetweentheSERDES101interfaceandthesystemcorelogicmaybesynthesizedandmappedtoastructuresuchasanASICorFPGAlocatedwithinthedatapathtocompensateforthisclockmismatch.However,ifthesameserialinterfaceontheSERDES101receivesan8bitdatastreamclockedat1GHz,thenthesystemcorelogicneedstobeclockedat500MHztoproperlyprocessacorresponding16bitdatastream.CurrentASICandFPGAtechnologyisunabletocosteffectivelyprovideanASICorFPGAthatachievestherequiredclockingspeedof500MHzoraboveforcorelogicprocessing.Inordertoincreasetherequireddatarateatthesystemcorelogic,thewidthoftheparalleldatabusmaybeexpandedbyafactoroftwo.Consequently,inthisparticularexample,theparalleldatabusmaybeexpandedto64bitorwidertoreducetherequiredinternalcorelogicclockingspeed.Theprincipleofexpandingparalleldatabuswidthmaybeextrapolatedtoachievehigherdatarateswithouthavingtoincreaseacorrespondingclockingspeed.Forexample,the64bitparallelbuscouldbechangedtoa128bitor256bittoreducetheclockfrequencyof500MHztohalforonefourthrespectively.Onecurrentsolutioninwhichvariablewidthdatabusesareprovidedisbygeneratingmultiplesystemdesignversionsinwhichdifferentinputsandclockfrequenciesareassociatedwitheachclockingspeedandinput.However,creatingmultipleversionofasystemdesignmaybecomelogisticallydifficultbecauseofthecreationandmaintenanceofmultiplesourcecodesrelatedtothedesign.Further,theverificationenvironmentandprocessmaybecomeoverlycomplicatedwhichmayrequiresupportengineerstoupdatepatchesformultiplecustomersusingdifferentversionsofthesystemdesign.Thereforethereisaneedforprovidingasinglesystemdesignthatallowsmultipleparalleldatawidthsandclockinputsinordertofacilitatethespeedmatchingofacomponent,suchascorelogic,totheserialinterfaceofaSERDESorothercomponent.SUMMARYOFTHEINVENTIONAsystem,apparatusandmethodthatprovidedatamanagementbetweenaserialinterfaceandothercomponentaredescribed.Inoneembodiment,thepresentinventionmaymanageadatastreambetweenaSERDESandatransceiver.AvariablelengthserialdatastreamisreceivedatabuffermanagerlocatedbetweentheSERDESandtransceiver.Thedatawithinthebuffermanageriscontrolledbyastatemachinethatisadvancedbyeventschedulerlogic.Theeventscheduler
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